Thin film transistor array panel and method of manufacturing the same

ABSTRACT

A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.

CLAIM PRIORITY

This application claims priority to and the benefit of Korean PatentApplication No. 10-2015-0000226 filed in the Korean IntellectualProperty Office on Jan. 2, 2015, the entire contents of which areincorporated herein by reference, and this application is filed pursuantto 35 U.S.C. §121 as a Divisional application of Applicants' PatentApplication Ser. No. 14/841,559 filed in the U.S. Patent & TrademarkOffice on 31 Aug. 2015, and assigned to the assignee of the presentinvention. All benefits accruing under 35 U.S.C. §120 from the aforesaidpresent application Ser. No. 14/841,559 are also claimed.

BACKGROUND 1. Field of Invention

The present invention generally relates to a thin film transistor arraypanel and a method of manufacturing the same.

2. Description of the Related Art

Generally, display devices such as a liquid crystal display and anorganic light emitting diode display include a plural pairs of fieldgenerating electrodes and an electro-optical active layer interposedtherebetween. The liquid crystal display includes a liquid crystal layeras the electro-optical active layer and the organic light emitting diodedisplay includes an organic emission layer as the electro-optical activelayer.

One of the pair of field generating electrodes is generally connected toa switching element to receive an electrical signal and theelectro-optical active layer converts the electrical signal into anoptical signal, thereby displaying an image.

The display device uses a thin film transistor (TFT) which is a threeterminal element as the switching device and includes signal lines, suchas a gate line which transfers a scanning signal for controlling thethin film transistor and a data line for transferring a signal to beapplied to a pixel electrode.

Meanwhile, as an area of the display device is increased, an oxidesemiconductor technology for realizing high speed driving has beenresearched and a method for reducing resistance of the signal line hasbeen researched. In particular, to reduce the resistance of the signalline, a main wiring layer may be made of materials such as copper orcopper alloy. In this case, porous metal oxide is formed between themain wiring layer and a passivation layer covering the main wiring layerand thus reliability of a device may be reduced.

The above information disclosed in this Related Art section is only forenhancement of understanding of the background of the invention andtherefore it may contain information that does not form the prior artthat is already known in this country to a person of ordinary skill inthe art.

SUMMARY

The present invention has been made in an effort to provide a thin filmtransistor array panel and a method of manufacturing the same havingadvantages of preventing porous metal oxide from being formed between amain wiring layer and a passivation layer.

An exemplary embodiment of the present invention provides a thin filmtransistor array panel including: a substrate; a gate electrode disposedon the substrate; a semiconductor layer disposed on the substrate; agate insulating layer disposed between the gate electrode and thesemiconductor layer; a source electrode disposed on the semiconductorlayer and a drain electrode facing the source electrode; a metal oxidelayer covering the source electrode and the drain electrode; and apassivation layer covering the source electrode, the drain electrode,and the metal oxide layer, wherein the source electrode and the drainelectrode include a first material and a second material which is addedto the first material and metal included in the metal oxide layer isformed by diffusing the second material.

The thin film transistor array panel may further include: a diffusionmetal layer disposed between the source electrode and the metal oxidelayer and between the drain electrode and the metal oxide layer.

The source electrode and the drain electrode may include copper orcopper alloy.

The second material may include at least one of Mn, Mg, Al, Mo, W, Ti,Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe.

The thin film transistor array panel may further include: barrier layersdisposed under the source electrode and the drain electrode, the barrierlayer including metal oxide.

The barrier layer may include one of indium-zinc oxide (IZO),gallium-zinc oxide (GZO), and aluminum-zinc oxide (AZO).

The metal oxide layer may cover upper surfaces and lateral walls of thesource electrode and the drain electrode, respectively.

The passivation layer may contact the upper surface and the lateral wallof the metal oxide layer.

The thin film transistor array panel may further include: barrier layersdisposed under the source electrode and the drain electrode; and cappinglayers disposed over the source electrode and the drain electrode, thebarrier layer and the capping layer including metal oxide.

Lateral walls of the source electrode and the drain electrode,respectively, which are adjacent to a channel region of thesemiconductor layer may be exposed and the exposed lateral wall of thesource electrode and the exposed lateral wall of the drain electrode maybe covered with the metal oxide layer.

The semiconductor layer may include oxide semiconductor.

The lateral wall of the semiconductor layer may be aligned like thelateral walls of the source electrode and the drain electrode, exceptfor the channel region.

Another embodiment of the present invention provides a method formanufacturing a thin film transistor array panel including: forming agate electrode on a substrate; forming a semiconductor layer on thesubstrate; forming a gate insulating layer between the gate electrodeand the semiconductor layer; forming a source electrode disposed on thesemiconductor layer and a drain electrode facing the source electrode;annealing the source electrode and the drain electrode; forming a metaloxide layer covering the source electrode and the drain electrode; andforming a passivation layer covering the source electrode, the drainelectrode, and the metal oxide layer, wherein the annealing includesdiffusing an alloyed material to surfaces of the source electrode andthe drain electrode.

The forming of the metal oxide layer may include performing nitrogenoxide plasma treating.

In the annealing, the diffusion metal layer may be formed between thesource electrode and the metal oxide layer and between the drainelectrode and the metal oxide layer and the diffusion metal layer mayinclude the alloyed material in the source electrode and the drainelectrode.

The method may further include: prior to the forming of the sourceelectrode and the drain electrode, forming a barrier layer on thesemiconductor layer, wherein the barrier layer is formed to include themetal oxide.

The metal oxide layer may be formed to cover upper surfaces and lateralwalls of the source electrode and the drain electrode, respectively.

The method may further include: prior to the forming of the sourceelectrode and the drain electrode, forming a barrier layer on thesemiconductor layer; and forming capping layers on the source electrodeand the drain electrode, wherein the barrier layer and the capping layerare formed to include the metal oxide.

The semiconductor layer may be formed to include oxide semiconductor.

The forming of the semiconductor layer and the forming of the sourceelectrode and the drain electrode may be simultaneously performed usingone mask.

According to an exemplary embodiment of the present invention, it ispossible to improve the reliability by suppressing the materials formingthe main wiring layer from being oxidized by forming the metal oxidelayer between the main wiring layer and the passivation layer. Further,according to an exemplary embodiment of the present invention, it ispossible to reduce the process costs by removing the capping layer whichis formed on the main wiring layer.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings, in which likereference symbols indicate the same or similar components, wherein:

FIG. 1 is a plan view illustrating a thin film transistor array panelaccording to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

FIGS. 3 to 13 are cross-sectional views illustrating a method ofmanufacturing of a thin film transistor array panel according to theexemplary embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a liquid display deviceaccording to an exemplary embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along the line II-II of FIG. 1to represent the thin film transistor array panel according to theexemplary embodiment of the present invention.

FIGS. 16 to 25 are cross-sectional views illustrating a method ofmanufacturing a thin film transistor array panel according to theexemplary embodiment of the present invention.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.However, the present invention is not limited to the exemplaryembodiments set forth herein but may be modified in many differentforms. On the contrary, exemplary embodiments introduced herein areprovided to make disclosed contents thorough and complete andsufficiently transfer the spirit of the present invention to thoseskilled in the art.

In the drawings, the thickness of layers, films, panels, regions, etc.,are exaggerated for clarity. Further, it will be understood that when alayer is referred to as being “on” another layer or substrate, it can bedirectly on the other layer or substrate, or intervening them may alsobe present. Like reference numerals designate like elements throughoutthe specification.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like or similar referencenumerals refer to like or similar elements throughout. As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers, patterns and/or sections, these elements, components, regions,layers, patterns and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer pattern or section from another region, layer, pattern or section.Thus, a first element, component, region, layer or section discussedbelow could be termed a second element, component, region, layer orsection without departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the example term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of theinvention. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments are described herein with reference to crosssectional illustrations that are schematic illustrations ofillustratively idealized example embodiments (and intermediatestructures) of the inventive concept. As such, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, exampleembodiments should not be construed as limited to the particular shapesof regions illustrated herein but are to include deviations in shapesthat result, for example, from manufacturing. The regions illustrated inthe figures are schematic in nature and their shapes are not intended toillustrate the actual shape of a region of a device and are not intendedto limit the scope of the inventive concept.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a plan view illustrating a thin film transistor array panelaccording to an exemplary embodiment of the present invention. FIG. 2 isa cross-sectional view taken along the line II-II of FIG. 1.

Referring to FIGS. 1 and 2, a thin film transistor array panel 100according to an exemplary embodiment of the present invention includes aplurality of gate lines 121 which are formed on an insulating substrate110 made of transparent glass, plastic, or the like.

The gate lines 121 transfers gate signals and mainly extend in ahorizontal direction. Each gate line 121 includes a plurality of gateelectrodes 124 which protrude from the gate lines 121.

The gate line 121 and the gate electrode 124 may have a double layerstructure which is configured of first layers 121 p and 124 p and secondlayers 121 q and 124 q. The first layers 121 p and 124 p and the secondlayers 121 q and 124 q each may be made of aluminum-based metals such asaluminum (Al) and aluminum alloy, silver-based metals such as silver(Ag) and silver alloy, copper-based metals such as copper (Cu) andcopper alloy, molybdenum-based metals such as molybdenum (Mo) andmolybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta), manganese(Mn), and the like. For example, the first layers 121 p and 124 p mayinclude titanium and the second layers 121 q and 124 q may includecopper or copper alloy.

The first layers 121 p and 124 p and the second layers 121 q and 124 qmay be formed by combining layers having different physical properties.The exemplary embodiment of the present invention describes that thegate line 121 and gate electrode 124 are formed in the double layer butis not limited thereto, and therefore the gate line 121 and gateelectrode 124 may be formed in a single layer form or a triple layerform.

A gate insulating layer 140 which is made of insulating materials suchas silicon oxide or silicon nitride is disposed on the gate line 121.The gate insulating layer 140 may include a first insulating layer 140 aand a second insulating layer 140 b. The first insulating layer 140 amay be made of silicon nitride (SiNx) having a thickness ofapproximately 4000 Å and the second insulating layer may be made ofsilicon oxide (SiOx) having a thickness of approximately 500 Å.According to another exemplary embodiment of the present invention, thefirst insulating layer 140 a may be made of silicon oxinitride (SiON)and the second insulating layer 140 b may be made of silicon oxide(SiOx). The exemplary embodiment of the present invention describes thatthe gate insulating layers 140 a and 140 b are formed in a double layerform, the gate insulating layers 140 a and 140 b may be formed in asingle layer form.

A semiconductor layer 151 is formed on the gate insulating layer 140.The semiconductor layer 151 may be made of amorphous silicon,crystalline silicon, or oxide semiconductor. The semiconductor layer 151mainly extends in a vertical direction and includes a pluralityprojections (154) which extend toward the gate electrode 124.

When the semiconductor layer 151 is made of the oxide semiconductor, thesemiconductor layer 151 includes at least one of zinc (Zn), indium (In),tin (Sn), gallium (Ga), and hafnium (Hf). In particular, according tothe exemplary embodiment of the present invention, the semiconductorlayer 151 may be made of indium-gallium-zinc oxide.

A data wiring layer which includes a plurality of data lines 171 and aplurality of source electrodes 173 and a plurality of drain electrodes175 which are connected to the data lines 171 is formed on thesemiconductor layer 151 and the gate insulating layer 140.

The data lines 171 transfer the data signals and mainly extend in avertical direction to intersect the gate lines 121. The source electrode173 extends from the data line 171 to overlap the gate electrode 124 andmay have substantially an U-letter shape. However, a structure of thesource electrode 173 and the drain electrode 175 may be modified.

The drain electrode 175 is separated from the data line 171 and extendsupward from a center of the U-letter shape of the source electrode 173.

The data line 171, the source electrode 173, and the drain electrode 175have a double layer structure of barrier layers 171 p, 173 p, and 175 pand main wiring layers 171 q, 173 q, and 175 q. The barrier layers 171p, 173 p, and 175 p are made of metal oxide. In detail, the barrierlayers 171 p, 173 p, and 175 p may be made of one of indium-zinc oxide,gallium-zinc oxide, and aluminum-zinc oxide. The barrier layers 171 p,173 p, and 175 p serve a diffusion preventing layer which preventsmaterials such as copper from being diffused to the semiconductor layer151.

The main wiring layers 171 q, 173 q, and 175 q include a first materialand a second material added thereto. For example, the first material maybe copper and the second material may include at least one of Mn, Mg,Al, Mo, W, Ti, Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe. The mainwiring layers 171 q, 173 q, and 175 q may be made of copper alloy. Thesecond material added to the first material may be equal to or less thanapproximately 20 at % of the entire content.

A diffusion metal layer 170 c is disposed on surfaces of the main wiringlayers 171 q, 173 q, and 175 q. According to the exemplary embodiment ofthe present invention, the diffusion metal layer 170 c may have a shapeenclosing the main wiring layers 171 q, 173 q, and 175 q. An material(second material) alloyed to the main wiring layers 171 q, 173 q, and175 q by annealing is diffused, so that the diffusion metal layer 170 cmay be formed.

According to the exemplary embodiment of the present invention, a metaloxide layer 177 is formed along an exposed surface of the diffusionmetal layer 170 c. The metal oxide layer 177 may be formed by beingoxidized in a state in which the diffusion metal layer 170 c is exposedto the outside. The diffusion metal layer 170 c may be oxidized bynitrogen oxide plasma treatment.

According to the exemplary embodiment of the present invention, themetal oxide layer 177 covers the source electrode 173 and the drainelectrode 175 while directly contacting the metal layers which aredisposed on the surfaces of the source electrode 173 and the drainelectrode 175, in particular, covers exposed lateral wall portions A andB of the source electrode 173 and the drain electrode 175 and exposedupper surfaces of the source electrode 173 and the drain electrode 175.In this case, the metal oxide layer 177 may not be formed on a portionof the gate insulating layer 140 which does not overlap the sourceelectrode 173 and the drain electrode 175 and on a channel region of thesemiconductor layer 151.

Hereinafter, the exposed lateral wall portion A of the source electrode173 and the drain electrode 175 which are adjacent to the channel regionof the semiconductor layer 151 will be described in detail.

Referring to FIG. 2, the projection 154 of the semiconductor layer 151is provided with a portion which is not covered with the data line 171and the drain electrode 175 and is exposed between the source electrode173 and the drain electrode 175. The semiconductor layer 151 may havesubstantially the same plane pattern as the data line 171 and the drainelectrode 175, except for the exposed portion of the projection 154. Inother words, a lateral wall of the semiconductor layer 151 may bealigned like a lateral wall of the data line 171, a lateral wall of thesource electrode 173, and a lateral wall of the drain electrode 175,except for the exposed portion of the projection 154.

One gate electrode 124, one source electrode 173, and one drainelectrode 175 form one thin film transistor (TFT) along with theprojection 154 of the semiconductor layer 151 and the channel region ofthe thin film transistor is formed at the projection 154 between thesource electrode 173 and the drain electrode 175.

The lateral walls of the source electrode 173 and the drain electrode175 which are adjacent to the channel region are exposed, the exposedside portions A of the source electrode 173 and the drain electrode 175are provided with the diffusion metal layer 170 c, and the exposed sideportions A of the source electrode 173 and the drain electrode 175 arecovered with the metal oxide layer 177.

When a subsequent process forming the passivation layer includingsilicon oxide in the state in which the lateral wall portions A of thesource electrode 173 and the drain electrode 175 without the diffusionmetal layer 170 c and the metal oxide layer 177 are exposed is performedor the projection 154 of the semiconductor layer is annealed to havechannel characteristics, materials such as copper included in the mainwiring layers 171 q, 173 q, and 175 q form porous oxide, and thuscharacteristics of the thin film transistor may be reduced. According tothe exemplary embodiment of the present invention, the metal oxide layer177 formed by the oxidization of the diffusion metal layer 170 c and thediffusion metal layer 170 c may prevent the materials such as copperfrom being oxidized.

A passivation layer 180 is formed on the source electrode 173, the drainelectrode 175, and the metal oxide layer 177. The passivation layer 180is made of inorganic insulating materials such as silicon nitride andsilicon oxide, organic insulating materials, insulating materials havinga low dielectric constant, and the like.

According to the exemplary embodiment of the present invention, thepassivation layer 180 may include a lower passivation layer 180 a and anupper passivation layer 180 b. The lower passivation layer 180 a may bemade of silicon oxide and the upper passivation layer 180 b may be madeof silicon nitride. According to the exemplary embodiment of the presentinvention, since the semiconductor layer 151 includes oxidesemiconductor, the lower passivation layer 180 a which is adjacent tothe semiconductor layer 151 may be made of silicon oxide. The lowerpassivation layer 180 a is made of silicon nitride, characteristics ofthe thin film transistor do not appear well.

The passivation layer 180 may contact a portion which is not coveredwith source electrode 173 and drain electrode 175 and is exposed betweenthe source electrode 173 and the drain electrode 175.

The passivation layer 180 is formed with a plurality of contact holes185 through which one end of the drain electrode 175 is exposed.

A plurality of pixel electrodes 191 are formed on the passivation layer180. The pixel electrode 191 is physically and electrically connected tothe drain electrode through the contact hole 185 and is applied with adata voltage from the drain electrode 175.

The pixel electrode 191 may be made of transparent conductive materialssuch as ITO or IZO.

FIGS. 3 to 13 are cross-sectional views illustrating a method ofmanufacturing of a thin film transistor array panel according to theexemplary embodiment of the present invention. FIGS. 3 to 13sequentially illustrate cross-sectional views taken along the cut lineII-II of FIG. 1.

Referring to FIG. 3, at least one of molybdenum-based metals such asmolybdenum (Mo) and molybdenum alloy, chromium (Cr), chromium alloy,titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, manganese(Mn), manganese alloy is staked on the insulating substrate 110 made oftransparent glass, plastic, or the like and one selected fromaluminum-based metals such as aluminum (Al) and aluminum alloy,silver-based metals such as silver (Ag) and silver alloy, andcopper-based metals such as copper (Cu) and copper alloy is stackedthereon to form the double layer and then pattern the double layer,thereby forming the gate line 121 including the gate electrode 124. Forexample, the lower layers 121 p and 124 p may include titanium and theupper layers 121 q and 124 q may include copper or copper alloy.

In detail, after the double layer is formed, a photo resist (not shown)is stacked and patterned and then the patterned photo resist (not shown)is used as a mask to etch the lower layers 121 p and 124 p and the upperlayers 121 q and 124 q together. In this case, as a usable etchant, anetchant which may etch the lower layers 121 p and 124 p and the upperlayers 121 q and 124 q together may be used.

Referring to FIG. 4, the gate insulating layer 140, the oxide layer 150,the metal oxide layer 170 p, and the metal layer 170 q are stacked onthe gate line 121 and the gate electrode 124. The first insulating layer140 a including silicon nitride is deposited on the gate insulatinglayer 140 and then the second insulating layer 140 b including siliconoxide including silicon oxide may be deposited thereon.

The oxide layer 150 may be formed to include at least one of zinc (Zn),indium (In), tin (Sn), gallium (Ga), and hafnium (Hf), the metal oxidelayer 170 p may be formed to include one of indium-zinc oxide,gallium-zinc oxide, and aluminum-zinc oxide, and the metal layer 170 qmay be formed to include copper alloy. The material included in coppermay include at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In, Ni, La, Nd,Sn, Ag, Cr, Zr, Zn, and Fe.

The photo resist is formed thereon and then is patterned to form a firstphoto resist pattern 50. The first photo resist pattern 50 has a thickfirst region 50 a and a relatively thinner second region 50 b. Adifference in thickness of the first photo resist pattern 50 may beformed by controlling an irradiated amount of light using the mask orusing a reflow method. In the case of controlling the amount of light, aslit pattern, a lattice pattern, or a translucent layer may be formed.The second region 50 b having a thin thickness corresponds to a positionat which the channel region of the thin film transistor is formed.

Referring to FIG. 5, the first photo resist pattern 50 is used as themask and an etchant which may etch the metal oxide layer 170 p and themetal layer 170 q together is used to etch the metal oxide layer 170 pand the metal layer 170 q. The etchant used herein may be the same asthe etchant used at the time of etching the lower layers 121 p and 124 pand the upper layers 121 q and 124 q of the gate line 121.

As illustrated in FIG. 5, when the metal oxide layer 170 p and the metallayer 1706 q are etched, the sides of the metal oxide layer 170 p andthe metal layer 170 q which are covered with the first photo resistpattern 50 are etched with the etchant, and as a result, as illustratedin FIG. 5, a boundary line between a first metal layer 170 p and asecond metal layer 170 r is disposed in regions A, B, and C in which thefirst photo resist pattern 50 is formed.

In this case, the etchant which etches the metal oxide layer 170 p andthe metal layer 170 q does not etch the gate insulating layer 140 andthe oxide layer 150.

In addition, the first photo resist pattern 50 uses the mask to etch theoxide layer 150.

Referring to FIG. 6, the second portion 50 b having a thin thickness inFIG. 5 is removed with an etch back. In this case, the first portion 50a is etched together and thus a width and a height thereof are reduced,and as a result, the first portion 50 a becomes a second photo resist 51of FIG. 6. The second photo resist 51 is formed in narrower regions A′,B′, and C′ narrower than the regions A, B, and C in which the firstphoto resist in FIG. 5 is formed.

Referring to FIG. 7, the second photo resist 51 is used as the mask andthe etchant is used to etch the metal oxide layer 170 p and the metallayer 170 q.

In this case, the metal oxide layer 170 p and the metal layer 170 q areseparated from each other to form the data lines 171 p and 171 q, thesource electrodes 173 p and 173 q, and the drain electrodes 175 p and175 q of the double layer. Further, the semiconductor layer 151including the projection 154 which forms the channel of the thin filmtransistor while the upper surface of the oxide layer 150 is exposed isformed.

As such, when the photo resists having different thicknesses are used,the semiconductor layers 151 and 154 having substantially the same planepattern as the barrier layers 171 p, 173 p, and 175 p and the mainwiring layers 171 q, 173 q, and 175 q of the data line 171, the sourceelectrode 173, and the drain electrode 175 are formed. In detail, thelateral walls of the semiconductor layers 151 and 154 are aligned to besubstantially same as the lateral wall of the data line 171, the lateralwall of the source electrode 173, and the lateral wall of the drainelectrode 175, except the exposed portion between the drain electrode175 and the source electrode 173.

Next, referring to FIG. 8, ashing is performed to remove the photoresist and then annealing may be performed to form the diffusion metallayer on the surfaces of the source electrode 173 and the drainelectrode 175.

Referring to FIG. 9, the second material (alloyed material) included inthe source part 173 q of the main wiring layer and the drain part 175 qof the main wiring layer are diffused to an edge during the annealing.In this case, copper is mainly distributed at the centers of the sourcepart 173 q of the main wiring layer and the drain part 175 q of the mainwiring layer and the diffusion metal layer 170 c including the secondmaterial is formed along the surfaces of the source part 173 q of themain wiring layer and the drain part 175 q of the main wiring layer.

Referring to FIG. 10, the surface of the diffusion metal layer 170 c maybe subjected to N2O (nitrous oxide) plasma treatment to improvecharacteristics of the thin film transistor.

Referring to FIG. 11, a portion of the diffusion metal layer 170 c whichis disposed on the surfaces of the source part 173 q of the main wiringlayer and the drain part 715 q of the main wiring layer is oxidized andthus the metal oxide layer 177 is formed along the surfaces thereof. Themetal oxide layer 177 may be formed on the upper surface and the lateralwall of the diffusion metal layer 170 c.

Referring to FIGS. 12 and 13, the passivation layer 180 is formed on themetal oxide layer 177, the gate insulating layer 140, and the projection154 of the semiconductor layer exposed between the source electrode 173and the drain electrode 175. The passivation layer 180 forms the lowerpassivation layer 180 a including silicon oxide (SiOx) and the upperpassivation layer 180 b including silicon nitride (SiNx) may be formedon the lower passivation layer 180 a.

The thin film transistor array panel as illustrated in FIG. 2 may beformed by forming the contact hole 185 through which a portion of thedrain electrode 175 is exposed by patterning the passivation layer 180and forming the pixel electrode 191 on the passivation layer 180. Inthis case, the pixel electrode 191 is formed to be physically connectedto the drain electrode 175 through the contact hole 185.

FIG. 14 is a cross-sectional view illustrating a liquid display deviceaccording to an exemplary embodiment of the present invention.

Referring to FIG. 14, the thin film transistor array panel 100 and thecounter display panel 200 face each other and the liquid crystal layer 3is disposed therebetween.

The second substrate 210 is disposed at a position facing the firstsubstrate 110. The second substrate 210 may be the insulating substratemade of transparent glass, plastic, or the like. The light blockingmember 220 is formed on the second insulating substrate 210. The lightblocking member 220 is called a black matrix and prevents light leakage.

A plurality of color filters 230 are formed on the second substrate 210and the light blocking member 220. The color filter 230 is mainlypresent in the region which is enclosed with the light blocking member220 and may vertically extend along a column of the pixel electrode 191.Each color filter 230 may display one of primary colors such as threeprimary colors of red, green, and blue. However, the color filters 230and 230′ may also display one of cyan, magenta, yellow, white-basedcolors, without being limited to the three primary colors of red, green,and blue.

Although the case in which the light blocking member 220 and the colorfilter 230 are formed on the counter display panel 200 is describedabove, but at least one of the light blocking member 220 and the colorfilter 230 may also be formed on the thin film transistor array panel100.

The overcoat 250 is formed on the color filter 230 and the lightblocking member 220. The overcoat 250 may be made of an insulatingmaterial and prevents the color filter 230 from being exposed andprovides a flat surface. The overcoat 250 may be omitted.

A common electrode 270 is formed on the overcoat 250.

The pixel electrode 191 to which the data voltage is applied generatesan electric field along with the common electrode 270 to which a commonvoltage is applied to determine an alignment of liquid crystal molecules31 of the liquid crystal layer 3 between the two electrodes. The pixelelectrode 191 and the common electrode 270 form a capacitor and thusmaintain an applied voltage even after the thin film transistor isturned off.

The pixel electrode 191 may overlap a storage electrode line (notillustrated) to form a storage capacitor, and thus voltage maintainingcapability of a liquid crystal capacitor may be strengthened.

The content of the exemplary embodiment described with reference to FIG.2 may be applied to the description of the thin film transistor arraypanel 100.

Although the case in which the thin film transistor array panelaccording to the exemplary embodiment of the present invention isapplied to the liquid crystal display is described, the exemplaryembodiment of the present invention may be widely applied to displaydevices which perform a switching operation using the organic lightemitting diode display and other thin film transistors.

FIG. 15 is a cross-sectional view taken along the line II-II of FIG. 1to represent the thin film transistor array panel according to theexemplary embodiment of the present invention.

The exemplary embodiment of the present invention described withreference to FIG. 15 is substantially the same as the exemplaryembodiment described with reference to FIG. 2. Hereinafter, portionsdifferent from the exemplary embodiment of the present invention of FIG.2 will be described.

Referring to FIG. 15, the data line 171, the source electrode 173, andthe drain electrode 175 further include capping layers 171 r, 173 r, and175 r which are disposed on the main wiring layers 171 q, 173 q, and 175q. The capping layers 171 r, 173 r, and 175 r include metal oxide. Forexample, the capping layers 171 r, 173 r, and 175 r may be made of oneof indium-zinc oxide, gallium-zinc oxide, and aluminum-zinc oxide andamong those, may be preferably made of gallium-zinc oxide. According tothe exemplary embodiment of the present invention, the metal oxide layer177 may be formed at the exposed lateral wall portions of the mainwiring layers 171, 173 q, and 175 r between the barrier layers 171 p,173 p, and 175 p and the capping layers 171 r, 173 r, and 175 r.

Except for the difference from the foregoing description, the contentdescribed with reference to FIG. 2 may be applied to all of theexemplary embodiments of the present invention.

FIGS. 16 to 25 are cross-sectional views illustrating a method ofmanufacturing a thin film transistor array panel according to theexemplary embodiment of the present invention. FIGS. 16 to 25sequentially illustrate cross-sectional views taken along the cut lineII-II of FIG. 1.

Referring to FIGS. 16 to 21, the method for manufacturing a thin filmtransistor array panel according to the exemplary embodiment of thepresent invention is substantially the same as the exemplary embodimentof the present invention described with reference to FIGS. 4 to 9.However, the method for manufacturing a thin film transistor array panelaccording to the exemplary embodiment of the present invention mayadditionally form the metal oxide layer 170 r on the metal layer 170 qas illustrated in FIG. 16. In the subsequent process, the metal oxidelayer 170 r is subjected to a patterning process along with the metallayer 170 q and the metal oxide layer 170 p which are formed thereunderto form the capping layers 171 r, 173 r, and 175 r on the main wiringlayers 171 q, 173 q, and 175 q as illustrated in FIG. 19.

Referring to FIG. 20, the ashing is performed to remove the photo resistand then the annealing may be performed to form the diffusion metallayer on the surfaces of the source electrode 173 and the drainelectrode 175.

Referring to FIG. 21, the second material (alloyed material) included inthe source part 173 q of the main wiring layer and the drain part 175 qof the main wiring layer are diffused to an edge during the annealing.In this case, copper is mainly distributed at the centers of the sourcepart 173 q of the main wiring layer and the drain part 175 q of the mainwiring layer and the diffusion metal layer 170 c including the secondmaterial is formed along the surfaces of the source part 173 q of themain wiring layer and the drain part 175 q of the main wiring surface.

Referring to FIG. 22, the surface of the diffusion metal layer 170 c maybe subjected to N2 O (nitrous oxide) plasma treatment to improvecharacteristics of the thin film transistor.

Referring to FIG. 23, a portion of the diffusion metal layer 170 c whichis disposed on the surfaces of the source part 173 q of the main wiringlayer and the drain part 715 q of the main wiring layer is oxidized andthus the metal oxide layer 177 is formed along the surfaces thereof. Themetal oxide layer 177 may be formed on the lateral wall of the diffusionmetal layer 170 c.

Referring to FIGS. 24 and 25, the passivation layer 180 is formed on themetal oxide layer 177, the gate insulating layer 140, the capping layers171 r, 173 r, and 175 r, and the projection 154 of the semiconductorlayer exposed between the source electrode 173 and the drain electrode175. The passivation layer 180 forms the lower passivation layer 180 aincluding silicon oxide (SiOx) and the upper passivation layer 180 bincluding silicon nitride (SiNx) may be formed on the lower passivationlayer 180 a.

The thin film transistor array panel as illustrated in FIG. 15 may beformed by forming the contact hole 185 through which a portion of thedrain electrode 175 is exposed by patterning the passivation layer 180and forming the pixel electrode 191 on the passivation layer 180. Inthis case, the pixel electrode 191 is formed to be physically connectedto the drain electrode 175 through the contact hole 185.

While this invention has been described in connection with what ispresently considered to be practical exemplary embodiments, it is to beunderstood that the invention is not limited to the disclosedembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

What is claimed is:
 1. A method for manufacturing a thin film transistorarray panel, disposing a gate electrode on a substrate; disposing asemiconductor layer on the substrate; disposing a gate insulating layerbetween the gate electrode and the semiconductor layer; disposing asource electrode on the semiconductor layer and a drain electrode facingthe source electrode; forming a metal oxide layer covering the sourceelectrode and the drain electrode; disposing a diffusion metal layerbetween the source electrode and the metal oxide layer and between thedrain electrode and the metal oxide layer; and forming a passivationlayer covering the source electrode, the drain electrode, and the metaloxide layer, wherein the source electrode and the drain electrodeinclude a first material and a second material which is added to thefirst material and wherein metal included in the metal oxide layer isthe same as the second material.
 2. The method of claim 1, furthercomprised of forming the metal oxide layer to contact lateral walls ofthe diffusion metal layer.
 3. The method of claim 2, further comprisedof including copper or a copper alloy in the formation of the sourceelectrode and the drain electrode.
 4. The method of claim 3, furthercomprised of including at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In,Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe in the second material.
 5. Themethod of claim 4, further comprised of disposing barrier layers underthe source electrode and the drain electrode, the barrier layerincluding metal oxide.
 6. The method of claim 5, further comprised ofincluding one of indium-zinc oxide (IZO), gallium-zinc oxide (GZO), andaluminum-zinc oxide (AZO) in the barrier layer.
 7. The method of claim1, further comprised of forming the metal oxide layer to cover uppersurfaces and lateral walls of the source electrode and the drainelectrode, respectively.
 8. The method of claim 7, further comprised offorming the passivation layer to contact the upper surface and thelateral wall of the metal oxide layer.
 9. The method of claim 1, furthercomprising: disposing barrier layers under the source electrode and thedrain electrode; and disposing capping layers over the source electrodeand the drain electrode, the barrier layer and the capping layerincluding metal oxide.
 10. The method of claim 9, further comprised of:disposing lateral walls of the source electrode and the drain electrode,respectively, which are adjacent to a channel region of thesemiconductor layer to be exposed and, covering the exposed lateral wallof the source electrode and the exposed lateral wall of the drainelectrode with the metal oxide layer.
 11. The method of claim 1, furthercomprised of including an oxide semiconductor in the semiconductorlayer.
 12. The method of claim 1, further comprised of aligning thelateral wall of the semiconductor layer like the lateral walls of thesource electrode and the drain electrode, except for the channel region.13. A method for manufacturing a thin film transistor array panel,comprising: forming a gate electrode on a substrate; forming asemiconductor layer on the substrate; forming a gate insulating layerbetween the gate electrode and the semiconductor layer; forming a sourceelectrode disposed on the semiconductor layer and a drain electrodefacing the source electrode; annealing the source electrode and thedrain electrode; forming a metal oxide layer covering the sourceelectrode and the drain electrode; and forming a passivation layercovering the source electrode, the drain electrode, and the metal oxidelayer, wherein the annealing includes diffusing an alloyed material tosurfaces of the source electrode and the drain electrode.
 14. The methodof claim 13, subjecting the metal oxide layer to a treatment by nitrogenoxide when forming the metal oxide layer.
 15. The method of claim 14,wherein: in the annealing, the diffusion metal layer is formed betweenthe source electrode and the metal oxide layer and between the drainelectrode and the metal oxide layer, and the diffusion metal layerincludes the alloyed material in the source electrode and the drainelectrode.
 16. The method of claim 15, further comprised of prior to theforming of the source electrode and the drain electrode, forming abarrier layer on the semiconductor layer, wherein the barrier layer isformed to include the metal oxide.
 17. The method of claim 16, wherein:the metal oxide layer is formed to cover upper surfaces and lateralwalls of the source electrode and the drain electrode, respectively. 18.The method of claim 17, further comprising: prior to the formation ofthe source electrode and the drain electrode, forming a barrier layer onthe semiconductor layer; and forming capping layers on the sourceelectrode and the drain electrode, wherein the barrier layer and thecapping layer are formed to include the metal oxide.
 19. The method ofclaim 13, wherein: the semiconductor layer is formed to include an oxidesemiconductor.
 20. The method of claim 13, wherein: the forming of thesemiconductor layer and the forming of the source electrode and thedrain electrode are simultaneously performed using one mask.